Field of the Invention
The present invention relates to a control apparatus of a device having a power-saving mode.
Description of the Related Art
Against the background of an increasing interest in energy saving in recent years, laws relating to power saving of electronic equipment are established. For example, to the image processing apparatus, such as a copying machine and a printer, the International Energy Star Program (image equipment standard), ErP (Energy related Products) regulation Lot6/Lot26, etc., are applied. In ErP regulation Lot26, the power consumption at the time of the network standby state from which electronic equipment can return triggered by remote access to the electronic equipment is regulated. In order to reduce the power consumption in the network standby state, it is considered to stop supply of power to a CPU.
In the case where supply of power to the CPU is stopped to bring about the power source cutoff state, it is necessary to perform power source cutoff control after performing reset control. Here, the reset control means to bring a register of a program counter or the like of the CPU into the initial state (hereinafter, called the reset state) by the CPU performing write access to a reset control module. Further, the power source cutoff control means to bring the CPU into the power source cutoff state by the CPU performing write access to a power source control module. In the case where the CPU enters the power source cutoff state, the main memory in which software that is executed by the CPU is developed also enters the power source cutoff state. Because of this, in the case where the power source cutoff control is performed without bringing the CPU into the reset state, the CPU starts its operation in the state where software that is executed by the CPU after the power source is turned on again is not developed, and therefore, the CPU will malfunction as a result. On the other hand, in the case where the CPU enters the reset state immediately after performing the reset control, the CPU cannot perform register access from then on, and therefore, it is no longer possible to perform the power source cutoff control.
Because of the above, severe restrictions are imposed on the timing of execution of commands of the reset control and the power source cutoff control that are performed by the CPU.
In order to implement the reset control and the power source cutoff control by satisfying the severe restrictions on the timing of the command execution, it is necessary for the CPU to successively fetch (acquire) instructions to perform the reset control and instructions to perform the power source cutoff control from a volatile memory, such as a Double-Data-Rate SDRAM (hereinafter, called a DDR memory) storing programs. Further, the DDR memory or the like is a volatile memory, and therefore, there is a possibility that the data contents will disappear in the case where a stimulus is not applied to the memory for a fixed period of time. In order to avoid the disappearance of data, a memory controller configured to control a volatile memory, such as a DDR memory, includes a mechanism to give instructions to cause the DDR memory to periodically refresh data (replenish charges) (see Japanese Patent Laid-Open No. 2012-133454).
In the case where the volatile memory performs a refresh operation at the time of the CPU fetching the instructions to perform the reset control and the instructions to perform the power source cutoff control from the volatile memory in order to make a transition into the network standby state (=power-saving state) described previously, it is not possible to successively fetch the above-described two instructions.
Consequently, an object of the present invention is to prevent a memory, which performs the refresh operation in order to avoid the disappearance of information, from performing the refresh operation at the timing at which the commands are fetched in the case where the instructions of the reset control and the power source cutoff control are fetched from the memory.